Siemens Digital Industries Software announced today the launch of Tessent™ IJTAG Pro, a breakthrough software set to transform IJTAG (IEEE 1687) input/output operations. The software enables parallel operations in what has traditionally been a serial process and provides read and write access to custom hardware, significantly enhancing testing flexibility for semiconductor designs.
Tessent IJTAG Pro introduces high-bandwidth internal JTAG (IJTAG) and generic data streaming functionality, leveraging the wide bus of Siemens’ Tessent Streaming Scan Network (SSN) software. These features help customers reduce both test costs and time by accelerating data transfer and optimizing existing testing infrastructure.
The announcement comes at a critical time for the semiconductor industry, which is undergoing unprecedented evolution as transistor density increases across multiple dimensions. As designs advance from 2D to 2.5D and full 3D IC architectures, testing challenges have multiplied. Rising test pattern counts, longer pattern application times, high Automatic Test Equipment (ATE) costs, and limited accessibility to test pins have made optimizing infrastructure for test scaling essential for maintaining a competitive edge in the design process.
With Tessent IJTAG Pro, Siemens provides a powerful solution for tackling these complex testing challenges while accelerating design validation and ensuring efficiency across modern semiconductor workflows.
“In today’s complex IC designs, test time optimization is a significant challenge. By utilizing Siemens’ SSN architecture to convert traditional serial IJTAG operations into high-bandwidth parallel processes, Tessent IJTAG Pro not only accelerates test and reduces cost associated with test but also provides flexibility needed for revolutionizing test access to meet the industry’s evolving needs,” said Ankur Gupta, Senior Vice President and General Manager, DDCP, Siemens Digital Industries Software. “As semiconductor design is scaling from simple 2D into full 3D IC architectures, test cost savings will be applicable in each chiplet as well as the entire 3D IC package.”
Srinivas Vooka, Senior Engineering Manager, Google, said, “High-Bandwidth IJTAG innovatively leverages the SSN bus architecture, and delivers patterns much faster than traditional serial methods, leading to substantial reduction in test application time, especially for BIST & Mixed Signal IP testing.”
The combination of the features in IJTAG Pro along with the recent announcement of Siemens’ Tessent™ AnalogTest software marks a significant expansion of capabilities and bandwidth.
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